About Me

• I completed Ph.D. in August 2023, titled "IP Core Protection and Detective Control of Data-intensive Hardware IPs against Piracy," at the Department of Computer Science & Engineering, Indian Institute of Technology (IIT) Indore, INDIA, under the supervision of Prof. Anirban Sengupta.
• My doctoral dissertation work focuses on developing robust and efficient solutions for hardware security while also creating secure and cost-effective hardware accelerators tailored for computationally intensive application frameworks using High-Level Synthesis (HLS).
• I worked as a Post-Doc researcher (Aug 2023-June 2024) under Translational research fellowship at IIT Indore to commercialize my PhD research work. We developed a ‘Hardware Security CAD Software platform’ named "SOFTDEEP" available publicly via CAD for Assurance initiative.
• I joined IIIT Bhopal as an Assistant Professor in the Department of Computer Science and Engineering on August 23, 2024. I aim to contribute to education, research, and innovation.
• Currently exploring secure and efficient hardware accelerators for healthcare, ML, multimedia, DSP and IoT, along with biometrics and quantum/blockchain-integrated hardware security.

Research Interests

• Hardware security
• Trustworthy Integrated Circuit (IC) design
• High-level Synthesis
• Hardware Architectural Optimization
• Hardware Acceleration
• Electronic Design Automation (EDA) for secure chips and systems
• Biometric Constraints based Hardware Intellectual Property (IP) Watermarking

Gallery

"MP Young Scientist" Award-2K23

2023-03-17

Best Paper Award "IEEE-iSeS-2022"

2022-12-19

News

• [2025-01-01] Secure Implantable Cardiac Pacemaker for Medical Consumer Electronics, Nature - npj Biomedical Innovations, Accepted
• [2024-12-01] Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications, Proceedings of 10th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), Accepted
• [2024-12-01] SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification, Proceedings of 10th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES), Accepted
• [2024-10-01] Joined as a Chapter Secretary, IEEE Consumer Technology Society (CTSoc) chapter, MP Section
• [2024-09-01] HLS Based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature, 37th IEEE International System-on-Chip Conference (IEEE- SOCC), Dresden, Germany
• [2024-08-01] Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP against Piracy, Springer Nature Computer Science (SNCS), Accepted
• [2020-02-01] Our project, "Hardware-Assisted Systems for AMR Diagnostics, has been approved under the PAIR (Partnerships for Accelerated Innovation and Research) programme by the ANRF (Anusandhan National Research Foundation). It has received a grant of ~₹50Lakhs.

Events

• Attended IEEE- iSES, 2024, as session chair, held in New Delhi, INDIA [2024-12-16]
• Attended 37th International Conference on VLSI Design (VLSID-2024), for presenting the research work “HLS based Hardware Security and IP Protection,” SRF, Kolkata, INDIA [2024-01-06]
• Attended 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2023), presented work at Juan-Les-Pins, France [2023-10-03]
• Attended and presented a paper in AsianHOST, 2023, held in Tianjin, China [2023-12-13]
• Attended and presented two papers in IEEE- iSES, 2023, held in Ahmedabad, INDIA [2023-12-18]

Curriculum Vitae

You can download a current copy of my CV here:

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