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Dr. Rahul Chaurasia

Assistant Professor

Indian Institute of Information Technology, Bhopal

Publications

Total: 45 • Conferences: 15 • Journals: 16 • Books/Chapters: 12 • Projects/Thesis: 2

Conferences

Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications
2024 IEEE International Symposium on Smart Electronic Systems (iSES)

Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications

Rahul Chaurasia, Anirban Sengupta

2024 IEEE International Symposium on Smart Electronic Systems (iSES) — 2024

SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification
2024 IEEE International Symposium on Smart Electronic Systems (iSES)

SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification

Anirban Sengupta, Rahul Chaurasia

2024 IEEE International Symposium on Smart Electronic Systems (iSES) — 2024

Securing Reusable Hardware IP cores using Palmprint Biometric
2021 IEEE International Symposium on Smart Electronic Systems (iSES)

Securing Reusable Hardware IP cores using Palmprint Biometric

R. Chaurasia and A. Sengupta

2021 IEEE International Symposium on Smart Electronic Systems (iSES) — 2021

Crypto-Genome Signature for Securing Hardware Accelerators
2022 IEEE 19th India Council International Conference (INDICON)

Crypto-Genome Signature for Securing Hardware Accelerators

R. Chaurasia and A. Sengupta

2022 IEEE 19th India Council International Conference (INDICON) — 2022

Protecting Trojan Secured DSP cores against IP piracy using Facial Biometrics
2022 IEEE 19th India Council International Conference (INDICON)

Protecting Trojan Secured DSP cores against IP piracy using Facial Biometrics

R. Chaurasia and A. Sengupta

2022 IEEE 19th India Council International Conference (INDICON) — 2022

Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core
2022 IEEE International Symposium on Smart Electronic Systems (iSES)

Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core

R. Chaurasia and A. Sengupta

2022 IEEE International Symposium on Smart Electronic Systems (iSES) — 2022

Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing
2022 IEEE International Symposium on Smart Electronic Systems (iSES)

Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing

R. Chaurasia and A. Sengupta

2022 IEEE International Symposium on Smart Electronic Systems (iSES) — 2022

Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template

R. Chaurasia, A. Reddy Asireddy and A. Sengupta

2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) — 2023

Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics
2023 IEEE International Symposium on Smart Electronic Systems (iSES)

Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics

R. Chaurasia, A. Sengupta

2023 IEEE International Symposium on Smart Electronic Systems (iSES) — 2023

Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample
2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)

Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample

A. Sengupta, R. Chaurasia, and A. Anshul

2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) — 2023

Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure
2023 IEEE International Symposium on Smart Electronic Systems (iSES)

Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure

A. Sengupta, R. Chaurasia

2023 IEEE International Symposium on Smart Electronic Systems (iSES) — 2023

SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks
2024 IEEE International Symposium on Smart Electronic Systems (iSES)

SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks

R. Chaurasia

2024 IEEE International Symposium on Smart Electronic Systems (iSES) — 2024

HLS based Hardware Security and IP Protection
37th International Conference on VLSI Design (VLSID)- SRF

HLS based Hardware Security and IP Protection

R. Chaurasia

37th International Conference on VLSI Design (VLSID)- SRF — 2024

Accepted
HLS Based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature
37th IEEE International System-on-Chip Conference (SOCC)

HLS Based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature

Vishal Chourasia, Anirban Sengupta, Rahul Chaurasia

37th IEEE International System-on-Chip Conference (SOCC) — 2024

Accepted
Blockchain based Pharmaceutical Supply Chain and its Challenges: A Review and Proposed Solution
2023 IEEE International Conference on ICT in Business Industry & Government (ICTBIG)

Blockchain based Pharmaceutical Supply Chain and its Challenges: A Review and Proposed Solution

U. K. Sahu, A. Jain, R. Chaurasia and K. K. Hiran

2023 IEEE International Conference on ICT in Business Industry & Government (ICTBIG) — 2023

Journals

Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems
IEEE Trans. Consum. Electron.

Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems

A. Sengupta, R. Chaurasia and T. Reddy

IEEE Trans. Consum. Electron. — 2021

Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric
IEEE Trans. Consum. Electron.

Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric

A. Sengupta and R. Chaurasia

IEEE Trans. Consum. Electron. — 2022

Retinal Biometric for Securing JPEG-Codec Hardware IP core for CE systems
IEEE Trans. Consum. Electron.

Retinal Biometric for Securing JPEG-Codec Hardware IP core for CE systems

R. Chaurasia and A. Sengupta

IEEE Trans. Consum. Electron. — 2023

Robust Security of Hardware Accelerators using Protein Molecular Biometric Signature and Facial Biometric Encryption Key
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.

Robust Security of Hardware Accelerators using Protein Molecular Biometric Signature and Facial Biometric Encryption Key

A. Sengupta, R. Chaurasia and A. Anshul

IEEE Trans. Very Large Scale Integr. (VLSI) Syst. — 2023

Exploring Handwritten Signature Image Features for Hardware Security
IEEE Trans. Dependable Secure Comput. (TDSC)

Exploring Handwritten Signature Image Features for Hardware Security

M. Rathor, A. Sengupta, R. Chaurasia and A. Anshul

IEEE Trans. Dependable Secure Comput. (TDSC) — 2023

Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression
IEEE Access

Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression

A. Sengupta and R. Chaurasia

IEEE Access — 2022

Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems
IEEE Consum. Electron. Mag. (CEM)

Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems

R. Chaurasia, A. Anshul, A. Sengupta and S. Gupta

IEEE Consum. Electron. Mag. (CEM) — 2022

Secure FFT IP using C-way Partitioning-based Obfuscation and Fingerprint
IEEE Design & Test

Secure FFT IP using C-way Partitioning-based Obfuscation and Fingerprint

A. Sengupta and R. Chaurasia

IEEE Design & Test — 2024

Accepted
Quadruple Phase Watermarking during High Level Synthesis for Securing Reusable Hardware IP Cores
Elsevier Journal Comput. Electr. Eng.

Quadruple Phase Watermarking during High Level Synthesis for Securing Reusable Hardware IP Cores

M. Rathor, A. Anshul, K. Bharath, R. Chaurasia and A. Sengupta

Elsevier Journal Comput. Electr. Eng. — 2023

Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS
Integr. VLSI J

Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS

R. Chaurasia and A. Sengupta

Integr. VLSI J — 2023

Biometrics for Hardware Security and Trust: Discussion and Analysis
IT Professional

Biometrics for Hardware Security and Trust: Discussion and Analysis

A. Sengupta, M. Rathor and R. Chaurasia

IT Professional — 2023

HLS based Swarm Intelligence Driven Optimized Hardware IP Core for Linear Regression based Machine Learning
IET J. Eng.

HLS based Swarm Intelligence Driven Optimized Hardware IP Core for Linear Regression based Machine Learning

A. Sengupta, R. Chaurasia and M. Rathor

IET J. Eng. — 2023

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs
Elsevier Journal Comput. Electr. Eng.

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs

A. Sengupta, R. Chaurasia and K Bharath

Elsevier Journal Comput. Electr. Eng. — 2023

Exploration of Optimal Functional Trojan-Resistant Hardware Intellectual Property (IP) Core Designs during High Level Synthesis
Microprocessors and Microsystems

Exploration of Optimal Functional Trojan-Resistant Hardware Intellectual Property (IP) Core Designs during High Level Synthesis

A. Sengupta, A. Anshul, R. Chaurasia

Microprocessors and Microsystems — 2023

Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP against Piracy
Springer Nature Computer Science

Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP against Piracy

R. Chaurasia and A. Sengupta

Springer Nature Computer Science — 2024

Invited paper
Secure implantable cardiac pacemaker for medical consumer electronics
npj Biomed. Innov.

Secure implantable cardiac pacemaker for medical consumer electronics

A. Sengupta and Rahul Chaurasia

npj Biomed. Innov. — 2025

PDF

Books/Chapters

Secured Integrated Circuit (IC/IP) Design Flow
CRC Book "Nanoelectronics for Next-generation Integrated Circuits"

Secured Integrated Circuit (IC/IP) Design Flow

R. Chaurasia, A. Sengupta, P. Pradeeprao

CRC Book "Nanoelectronics for Next-generation Integrated Circuits" — 2022

Hardware IP Cores for Image Processing Functions
IOP Book “Advances in Image and Data Processing using VLSI Design"

Hardware IP Cores for Image Processing Functions

A. Sengupta and R. Chaurasia

IOP Book “Advances in Image and Data Processing using VLSI Design" — 2022

Integrated Defense using Structural obfuscation and Encrypted DNA based Biometric for Hardware Security
IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”

Integrated Defense using Structural obfuscation and Encrypted DNA based Biometric for Hardware Security

A. Sengupta and R. Chaurasia

IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors” — 2023

Facial Signature based Biometrics for Hardware Security and IP Core protection
IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”

Facial Signature based Biometrics for Hardware Security and IP Core protection

A. Sengupta and R. Chaurasia

IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors” — 2023

Secured Convolutional Layer Hardware Co-processor in Convolutional Neural Network (CNN) using Facial Biometric
IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”

Secured Convolutional Layer Hardware Co-processor in Convolutional Neural Network (CNN) using Facial Biometric

A. Sengupta and R. Chaurasia

IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors” — 2023

Handling Symmetrical IP Core Protection and IP Protection (IPP) of Trojan Secured Designs in HLS using Physical Biometrics
IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”

Handling Symmetrical IP Core Protection and IP Protection (IPP) of Trojan Secured Designs in HLS using Physical Biometrics

A. Sengupta and R. Chaurasia

IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors” — 2023

Methodology for Exploration of Security-Design Cost Tradeoff for Signature-based Security Algorithms
IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”

Methodology for Exploration of Security-Design Cost Tradeoff for Signature-based Security Algorithms

A. Sengupta and R. Chaurasia

IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors” — 2023

Securing Hardware Coprocessors against Piracy using Biometrics for Secured IoT systems
IET Book “Artificial Intelligence for Biometrics and Cybersecurity”

Securing Hardware Coprocessors against Piracy using Biometrics for Secured IoT systems

A. Anshul, R. Chaurasia and A. Sengupta

IET Book “Artificial Intelligence for Biometrics and Cybersecurity” — 2023

Introduction to High-Level Synthesis based Hardware Security and Trust: Goals and Challenges
IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”

Introduction to High-Level Synthesis based Hardware Security and Trust: Goals and Challenges

A. Sengupta and R. Chaurasia

IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection” — 2024

Accepted
High-Level Synthesis based Methodology for Securing Hardware IPs using Retinal Biometrics
IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”

High-Level Synthesis based Methodology for Securing Hardware IPs using Retinal Biometrics

A. Sengupta and R. Chaurasia

IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection” — 2024

Accepted
Hardware Obfuscation -High level Synthesis based Structural Obfuscation for Hardware Security and Trust
IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”

Hardware Obfuscation -High level Synthesis based Structural Obfuscation for Hardware Security and Trust

A. Sengupta and R. Chaurasia

IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection” — 2024

Accepted
Hardware Obfuscation-Algorithmic Transformation based Obfuscation for Secure Floorplan Driven High Level Synthesis
IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”

Hardware Obfuscation-Algorithmic Transformation based Obfuscation for Secure Floorplan Driven High Level Synthesis

A. Sengupta and R. Chaurasia

IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection” — 2024

Accepted

Projects/Thesis

IP Core Protection and Detective Control of Data Intensive Hardware IPs against Piracy
Indian Institute of Technology Indore

IP Core Protection and Detective Control of Data Intensive Hardware IPs against Piracy

Rahul Chaurasia, Anirban Sengupta

Indian Institute of Technology Indore — 2023

Doctor of Philosophy Thesis
SOFTDEEP: HLS based IP Protection tool for Secure Optimal Fault Tolerant Designs with Embedded Encrypted Protein signature
Indian Institute of Technology Indore

SOFTDEEP: HLS based IP Protection tool for Secure Optimal Fault Tolerant Designs with Embedded Encrypted Protein signature

Rahul Chaurasia, Anirban Sengupta

Indian Institute of Technology Indore — 2024

Post-Doc Translational Research
© 2026 Dr. Rahul Chaurasia — Assistant Professor
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